A p-channel MOS synapse transistor with self-convergent memory writes

We have developed a p-channel floating-gate-MOS synapse transistor for silicon-learning applications. The synapse stores a nonvolatile analog weight by means of charge on its floating gate, modifies this weight bidirectionally using electron tunneling and hot-electron injection, and allows simultaneous memory reading and writing. The synapse also learns locally-its weight updates depend only on the applied terminal voltages and on the stored weight. We fabricated an array of synapses that computed both the array output, and the weight updates, in parallel. We also demonstrated a self-convergent write procedure that permitted accurate initialization of the synapse weights. Our pFET synapse is small, and is operated at subthreshold current levels; it will permit the development of dense, low-power, silicon learning systems.

[1]  A. S. Grove Physics and Technology of Semiconductor Devices , 1967 .

[2]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[3]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[4]  T. H. Brown,et al.  Conductance mechanism responsible for long-term potentiation in monosynaptic and isolated excitatory synaptic inputs to hippocampus. , 1986, Journal of neurophysiology.

[5]  H. Melchior,et al.  A four-state EEPROM using floating-gate memory cells , 1987 .

[6]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[7]  T. A. DeMassa,et al.  Review of carrier injection in the silicon/silicon-dioxide system , 1991 .

[8]  Tetsuo Endoh,et al.  Reliability issues of flash memory cells , 1993, Proc. IEEE.

[9]  Carver Mead Scaling of MOS technology to submicrometer feature sizes , 1994, J. VLSI Signal Process..

[10]  E. Vittoz,et al.  An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .

[11]  Carver A. Mead,et al.  A single-transistor silicon synapse , 1996 .

[12]  Terrence J. Sejnowski,et al.  The Computational Brain , 1996, Artif. Intell..

[13]  H. Van Tran,et al.  A 2.5 V 256-level non-volatile analog storage device using EEPROM technology , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  S.S. Chung,et al.  Performance and reliability evaluations of p-channel flash memories with different programming schemes , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[15]  Carver A. Mead,et al.  A Complementary Pair of Four-Terminal Silicon Synapses , 1997 .

[16]  Paul Hasler,et al.  Floating-gate MOS synapse transistors , 1998 .