Delay locked loop of a semiconductor device and method of controlling the same

A delay lock that can adjust the on-time portion of the circuit or the entire circuit loop circuit is disclosed. The delay lock loop circuit includes a delay line, and a wait signal generating circuit. Wait signal generating circuit generates an active signal, a clock enable signal, a first CAS latency signal, and a second CAS signal and the first stand-second wait signal in response to a latency signal. The front stage circuit is disabled by comparing the phase of the external clock signal and a feedback signal and to generate a first clock signal by delaying the external clock signal based on the phase difference between the external clock signal and the feedback signal and the first response to the wait signal . Back-stage circuit is disabled to perform the interpolation of the duty cycle correction on the first clock signal and performs buffering and the second response to the wait signal.