A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis
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[1] Tao Jiang,et al. A 0.6mW/Gbps, 6.4–8.0Gbps serial link receiver using local injection-locked ring oscillators in 90nm CMOS , 2009, 2009 Symposium on VLSI Circuits.
[2] Muneo Fukaishi,et al. Oversampled Edge Equalization , 2005 .
[3] W. Beyene. Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems , 2007, 2007 IEEE Electrical Performance of Electronic Packaging.
[4] R. Mooney,et al. An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[5] M. Horowitz,et al. A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.
[6] Gu-Yeon Wei,et al. An 8$\,\times\,$ 5 Gb/s Parallel Receiver With Collaborative Timing Recovery , 2009, IEEE Journal of Solid-State Circuits.
[7] M. Takamiya,et al. 12Gb/s duobinary signaling with /spl times/2 oversampled edge equalization , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[8] J.E. Jaussi,et al. Modeling and Analysis of High-Speed I/O Links , 2009, IEEE Transactions on Advanced Packaging.
[9] Bryan Casper,et al. Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[10] Behzad Razavi. Design of intergrated circuits for optical communications , 2002 .
[11] William J. Dally,et al. The BlackWidow High-Radix Clos Network , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[12] S. Okwit,et al. ON SOLID-STATE CIRCUITS. , 1963 .
[13] James E. Jaussi,et al. Future Microprocessor Interfaces: Analysis, Design and Optimization , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[14] Patrick Chiang,et al. A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.
[15] Jri Lee,et al. Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data , 2008, IEEE Journal of Solid-State Circuits.
[16] John G. Proakis,et al. Digital Communications , 1983 .
[17] R. Mooney,et al. A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[18] Pavan Kumar Hanumolu,et al. Analysis of PLL clock jitter in high-speed serial links , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[19] Vladimir Stojanovic,et al. Modeling and analysis of high-speed links , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[20] James E. Jaussi,et al. 4.6 A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS , 2006 .
[21] A. Leon-Garcia,et al. Probability, statistics, and random processes for electrical engineering , 2008 .