A VHDL primer

1. Introduction. What Is VHDL? History. Capabilities. Hardware Abstraction. 2. A Tutorial. Basic Terminology. Entity Declaration. Architecture Body. Configuration Declaration. Package Declaration. Package Body. Model Analysis. Simulation. 3. Basic Language Elements. Identifiers. Data Objects. Data Types. Operators. 4. Behavioral Modeling. Entity Declaration. Architecture Body. Process Statement. Variable Assignment Statement. Signal Assignment Statement. Wait Statement. If Statement. Case Statement. Null Statement. Loop Statement. Exit Statement. Next Statement. Assertion Statement. Report Statement. More on Signal Assignment Statement. Other Sequential Statements. Multiple Processes. Postponed Processes. 5. Dataflow Modeling. Concurrent Signal Assignment Statement. Concurrent versus Sequential Signal Assignment. Delta Delay Revisited. Multiple Drivers. Conditional Signal Assignment Statement. Selected Signal Assignment Statement. The UNAFFECTED Value. Block Statement. Concurrent Assertion Statement. Value of a Signal. 6. Structural Modeling. An Example. Component Declaration. Component Instantiation. Other Examples. Resolving Signal Values. 7. Generics and Configurations. Generics. Why Configurations? Configuration Specification. Configuration Declaration. Default Rules. Conversion Functions. Direct Instantiation. Incremental Binding. 8. Subprograms and Overloading. Subprograms. Subprogram Overloading. Operator Overloading. Signatures. Default Values for Parameters. 9. Packages and Libraries. Package Declaration. Package Body. Design File. Design Libraries. Order of Analysis. Implicit Visibility. Explicit Visibility. 10. Advanced Features. Entity Statements. Generate Statements. Aliases. Qualified Expressions. Type Conversions. Guarded Signals. Attributes. Aggregate Targets. More on Block Statements. Shared Variables. Groups. More on Ports. 11. Model Simulation. Simulation. Writing a Test Bench. Converting Real and Integer to Time. Dumping Results into a Text File. Reading Vectors from a Text File. A Test Bench Example. Initializing a Memory. Variable File Names. 12. Hardware Modeling Examples. Modeling Entity Interfaces. Modeling Simple Elements. Different Styles of Modeling. Modeling Regular Structures. Modeling Delays. Modeling Conditional Operations. Modeling Synchronous Logic. State Machine Modeling. Interacting State Machines. Modeling a Moore FSM. Modeling a Mealy FSM. A Generic Priority Encoder. A Simplified Blackjack Program. A Clock Divider. A Generic Binary Multiplier. A Pulse Counter. A Barrel Shifter. Hierarchy in Design. Appendix A: Predefined Environment. Reserved Words. Package STANDARD. Package TEXTIO. Appendix B: Syntax Reference. Conventions. The Syntax. Appendix C: A Package Example. The Package ATT_MVL. Appendix D: Summary of Changes. VHDL-93 Features. Portability from VHDL-87. Appendix E: The STD_LOGIC_1164 Package. Package STD_LOGIC_1164. Appendix F: An Utility Package. Package UTILS_PKG. Bibliography. Index.