Polymorphic On-Chip Networks
暂无分享,去创建一个
[1] M. Coppola,et al. Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[2] William J. Dally,et al. Flattened Butterfly Topology for On-Chip Networks , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[3] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[4] W. Daniel Hillis,et al. The network architecture of the Connection Machine CM-5 (extended abstract) , 1992, SPAA '92.
[5] Alyssa B. Apsel,et al. Leveraging Optical Technology in Future Bus-based Chip Multiprocessors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[6] Alan Gatherer,et al. The Application of Programmable Dsps in Mobile Communications , 2002 .
[7] William J. Dally,et al. Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.
[8] Valentin Puente,et al. Rotary router: an efficient architecture for CMP interconnection networks , 2007, ISCA '07.
[9] L. Benini,et al. Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[10] William J. Dally,et al. A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.
[11] Edmond Chow,et al. A Scalable Distributed Parallel Breadth-First Search Algorithm on BlueGene/L , 2005, ACM/IEEE SC 2005 Conference (SC'05).
[12] William J. Dally,et al. Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[13] Simon W. Moore,et al. Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[14] Radu Marculescu,et al. System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Jaehyuk Huh,et al. Exploring the design space of future CMPs , 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.
[16] William J. Dally,et al. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.
[17] Fadi J. Kurdahi,et al. Morphosys: case study of a reconfigurable computing system targeting multimedia applications , 2000, Proceedings 37th Design Automation Conference.
[18] Luca Benini,et al. ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip , 2004, DATE.
[19] Scott A. Mahlke,et al. BulletProof: a defect-tolerant CMP switch architecture , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..
[20] Kunle Olukotun,et al. Maximizing CMP throughput with mediocre cores , 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).
[21] Partha Pratim Pande,et al. Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.
[22] George Varghese,et al. The Pleiades Architecture , 2002 .
[23] Carl Ebeling,et al. RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.
[24] Niraj K. Jha,et al. Express virtual channels: towards the ideal interconnection fabric , 2007, ISCA '07.
[25] Sharad Malik,et al. Power-driven Design of Router Microarchitectures in On-chip Networks , 2003, MICRO.
[26] William J. Dally,et al. Digital systems engineering , 1998 .