Design of tunable digital delay cells

This work discusses design considerations for implementing widely tunable delay cells with good matching properties, low jitter, and robust communication to adjacent circuits. Previously unreported effects that result in signal-dependent delay are discussed and eliminated. A 1.2 V 65 nm CMOS prototype achieves a tunability range from 5 ns to 10 μs, with a matching standard deviation of 2.3% and a jitter standard deviation of 0.065%.

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