Integral impact of BTI and voltage temperature variation on SRAM sense amplifier

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). A lot of work is published on the impact of BTI in SRAMs; however most of the work focused mainly on the memory cell array. An SRAM consists also of peripheral circuitries such as address decoders, sense amplifiers, etc. This paper characterizes the combined impact of BTI and voltage temperature fluctuations on the memory sense amplifier for different technology nodes (45nm up to 16nm). The evaluation metric, the sensing delay (SD), is analyzed for various workloads. In contrast to earlier work, this paper thoroughly quantifies the increased impact of BTI in such sense amplifiers for all the relevant technology scaling parameters. The results show that the BTI impact for nominal voltage and temperature is 6.7% for 45nm and 12.0% for 16nm when applying the worst case workload, while this is 1.8% for 45nm technology and 3.6% higher for 16nm when applying the best case workload. In addition, the results show that the increase in power supply significantly reduces the BTI degradation; e.g., the degradation at -10%Vdd is 9.0%, while this does not exceed 5.3% at +10%Vdd at room temperature. Moreover, the results that the increase in temperature can double the degradation; for instance, the degradation at room temperature and nominal Vdd is 6.7% while this goes up to 18.5% at 398K.

[1]  Rudy Lauwereins,et al.  BTI reliability from planar to FinFET nodes: Will the next node be more or less reliable? , 2014 .

[2]  Said Hamdioui,et al.  BTI impact on SRAM sense amplifier , 2013, 2013 8th IEEE Design and Test Symposium.

[3]  Michael Nicolaidis,et al.  Reliability challenges of real-time systems in forthcoming technology nodes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[5]  Robert C. Aitken,et al.  Impact of voltage scaling on nanoscale SRAM reliability , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Francky Catthoor,et al.  Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates , 2014, IEEE Transactions on Device and Materials Reliability.

[7]  F. Nouri,et al.  On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[8]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[9]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[10]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[11]  Ching-Te Chuang,et al.  Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability , 2009, Microelectron. Reliab..

[12]  Sachin S. Sapatnekar,et al.  Overcoming Variations in Nanometer-Scale Technologies , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[13]  Andrew R. Brown,et al.  Impact of NBTI/PBTI on SRAM Stability Degradation , 2011, IEEE Electron Device Letters.

[14]  Francky Catthoor,et al.  Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity , 2013, 2013 8th IEEE Design and Test Symposium.

[15]  Hamid Mahmoodi,et al.  Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[16]  Francky Catthoor,et al.  Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory , 2014, IEEE Transactions on Device and Materials Reliability.

[17]  G. Groeseneken,et al.  Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.

[18]  T. DeMassa,et al.  Threshold voltage variations with temperature in MOS transistors , 1971 .

[19]  Said Hamdioui.  Testing Static Random Access Memories: Defects, Fault Models and Test Patterns , 2004 .

[20]  C. Cabral,et al.  A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[21]  Kaushik Roy,et al.  Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[22]  Mile K. Stojcev.  Testing Static Random Access Memories: Defects, Fault Models and Test Patterns, Said Hamdioui, Kluwer Academic Publishers, Boston, 2004, Hardcover, pp 221, plus XX, ISBN 1-4020-7752-1 , 2005, Microelectron. Reliab..

[23]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[24]  Francky Catthoor,et al.  Bias Temperature Instability analysis of FinFET based SRAM cells , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Said Hamdioui.  Testing Static Random Access Memories , 2004 .

[26]  Stefan Cosemans,et al.  Variability-Aware Design of Low Power SRAM Memories (Variabiliteitsbewust ontwerp van SRAM geheugens met een zeer laag energieverbruik) , 2009 .

[27]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[28]  Antonio Rubio,et al.  Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime , 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

[29]  G. Groeseneken,et al.  From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[30]  A. Carlson.  Mechanism of Increase in SRAM $V_{\min}$ Due to Negative-Bias Temperature Instability , 2007, IEEE Transactions on Device and Materials Reliability.