A Scalable Video Rate Camera Interface

We survey the state of the art in high-speed interfaces for video input to high performance computers and note the difficulty of providing video at rates appropriate to modern parallel computers. Most interfaces that have been developed to date are not scalable, required extensive hardware development, and impose a full frame time delay between the moment the camera captures video and the moment it is available for processing. We propose a solution, based on a simple interface we have developed, which has been integrated into the iWarp parallel computer developed by Carnegie Mellon University and Intel Corporation. The interface takes advantage of iWarp''s systolic capabilities, does not impose any frame buffer delay time, was simple to design, and is readily scalable to provide up to 32 camera ports, from all of which data can be captured at full video rate, on a system that fits in a 19" 6U rack. We have applied the system to multibaseline stereo vision, and provide performance figures.

[1]  J. A. Webb Latency and bandwidth considerations in parallel robotics image processing , 1993, Supercomputing '93.

[2]  Keith Jack,et al.  Video Demystified: A Handbook for the Digital Engineer , 1993 .

[3]  Katsushi Ikeuchi,et al.  Determination of motion breakpoints in a task sequence from human hand motion , 1994, Proceedings of the 1994 IEEE International Conference on Robotics and Automation.

[4]  S. B. Kang,et al.  Recovering 3 D Shape and Motion from Image Streams using Non-Linear Least Squares , 1993 .

[5]  Volker Graefe,et al.  The Bvv-Family of Robot Vision Systems , 1990, Proceedings of the IEEE International Workshop on Intelligent Motion Control.

[6]  Takeo Kanade,et al.  A multiple-baseline stereo , 1991, Proceedings. 1991 IEEE Computer Society Conference on Computer Vision and Pattern Recognition.

[7]  Richard Szeliski,et al.  Recovering 3D Shape and Motion from Image Streams Using Nonlinear Least Squares , 1994, J. Vis. Commun. Image Represent..

[8]  Jake K. Aggarwal,et al.  Structure from stereo-a review , 1989, IEEE Trans. Syst. Man Cybern..

[9]  Gianni Conte,et al.  Massively Parallel Processor , 1994 .

[10]  H. T. Kung,et al.  Supporting systolic and memory communication in iWarp , 1990, ISCA '90.