Trends in high-performance microprocessor design

General-purpose microprocessors are the devices that have fueled the personal computer and internet revolution we have experienced over the past couple of decades. A processor is at the heart of every computer system in use today, from tiny autonomous embedded control systems to large scale, powerful, networked supercomputers. The Compaq Alpha microprocessor line fits into the highperformance end of this spectrum, powering high-end workstations, servers, and supercomputers. Over the years, processor architecture and design always had to respond to and move in lock-step with technological advances in processor implementation and integrated circuit technology, as well as programming paradigms and instructions sets. In this paper I review some of the trends that have driven the Compaq Alpha processor architecture in the past decade and give an outlook at current and future trends that will have an impact on the architecture of future Alpha processors. Introduction A processor is at the heart of every computer system that we build today. Around this processor, you find several other components that make up a computer. Memory for instruction and data storage and input-output devices to communicate with the rest of the world, like disk controllers, graphics cards, keyboard interfaces, network adapters, etc. The purpose of the processor is to execute machine instructions. Thus, the logical operation of a processor is defined by the instruction set architecture (ISA) that it executes. Multiple different processors can implement the same ISA. What differentiates such processors is their processor architecture, which is the way that each processor is organized internally in order to achieve the goal of implementing its ISA. By changing the processor architecture, a processor designer can influence the performance characteristics and efficiency with which instructions are executed. Processor architecture also has to respond to implementation constraints imposed on it by the target circuit technology of the chip, in order to achieve a set performance goal. In the rest of this section I will give a short crash course in advanced computer architecture an overview of the state of the art in processor architecture for general-purpose high-performance microprocessors. Early Architectures In early computer architectures, processor operation was very simple and strictly sequential. In the first step, for each instruction the program counter (PC) would be used to send the next instruction address to memory. Potentially several clock cycles later, the instruction is returned from memory. Then the instruction would be decoded. Decoding produces a list of source and destination operands that the instruction operates on, and a specific operation that is to be performed. In the next step, source operands would be accessed and delivered to the arithmetic-logic unit (ALU). The ALU eventually performs the operation that was specified in the instruction and delivers a result. The result is then written back to the destination that was decoded. Finally, the PC would be updated to advance to the next instruction that is to be executed, after which the whole process starts from the beginning for the next instruction. It is easy to see that in this type of design, many operations of the processor are unnecessarily serialized and large portions of the processor sit idle for a majority of time. For example, the ALU is only busy during the period where the operation is performed on the source operands, but sits idle during the rest of the time it takes to execute an instruction. It is not uncommon for an instruction to consume on the order of 10 clock cycles to execute. Processor architects often quote processor performance in instructions executed per clock cycle (IPC). Therefore, this simple processor architecture would achieve a performance of 0.1 IPC [4]. A driving force for this design were sparse resources. The number of transistors that was available on a processor chip was low (tens of thousands). Much emphasis of the design had to be placed on limiting the number of transistors to implement each function of the processor. Efficiency could only be addressed when functionality was satisfied, which left little freedom. Pipelining To achieve higher performance, the various operations involved in executing a single instruction can be separated into different stages of a pipeline and performed in parallel for multiple instructions. Since the pipeline can only advance at the rate of its slowest stage, it is advantageous for all instructions to have approximately the same amount of work to do in each pipeline stage. The architectural shift to a pipelined design goes hand in hand with a shift in predominant ISAs of the time from complex instruction sets (CISC) to simpler, reduced instruction sets (RISC). In RISC instruction sets, each instruction only performs a simple operation that can be executed in a short pipeline stage. All instructions have a similar amount of work to perform, supporting a shift to pipelined architectures. Artur Klauser TU Graz, Telematik, Dipl.-Ing. 1994 Univ. of Colorado at Boulder, Computer