FPGA implementation of Radix-2 2 pipelined FFT processor

The Fast Fourier Transform (FFT) is very important algorithm in signal processing, software-defined radio, and wireless communication. This paper explains the realization of radix-22 single-path delay feedback pipelined FFT processor. This architecture has the same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors (DSPs), and also can achieve cost effectively ASIC-like performance with lower development time, and risks. The processor has been developed using hardware description language VHDL and simulated up to 465 MHz on an Xilinx xc5vsx35t for transformation length 256-point.

[1]  Chin-Teng Lin,et al.  A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[2]  Juan F. Sevillano,et al.  An approach to simplify the design of IFFT/FFT cores for OFDM systems , 2006, IEEE Transactions on Consumer Electronics.

[3]  T. Sansaloni,et al.  Efficient pipeline FFT processors for WLAN MIMO-OFDM systems , 2005 .

[4]  Jeich Mar,et al.  Realization of OFDM Modulator and Demodulator for DSRC Vehicular Communication System Using FPGA Chip , 2006, 2006 International Symposium on Intelligent Signal Processing and Communications.

[5]  Mats Torkelson,et al.  A new approach to pipeline FFT processor , 1996, Proceedings of International Conference on Parallel Processing.

[6]  Juan F. Sevillano,et al.  An FFT Core for DVB-T/DVB-H Receivers , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[7]  Xuemei Liu,et al.  The Design of Radix-4 FFT by FPGA , 2008, 2008 International Symposium on Intelligent Information Technology Application Workshops.

[8]  J. C. Ebergen.  VLSI design , 1992, IEEE Des. Test Comput..

[9]  Liang Yang,et al.  An efficient locally pipelined FFT processor , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Juan A. Michell,et al.  FPGA realization of a split radix FFT processor , 2007, SPIE Microtechnologies.

[11]  Sau-Gee Chen,et al.  An efficient FFT twiddle factor generator , 2004, 2004 12th European Signal Processing Conference.