Design of Electronic Circuits Using a Divide-and-Conquer Approach

Automatic design of electronic logic circuits has become a new research focus with the cooperation of FPGA technology and intelligent algorithms in recent twenty years. However, as the size of logic circuits became larger and more complex, it has become difficult for the automatic design method to obtain valid and optimized circuits. Based on a divide-and-conquer approach, a two-layer encoding scheme was devised for design of electronic logic circuits. In the process of evolvement, each layer was evolved parallel and they contacted each other at the same time. Moreover, in order to simulate and evaluate evolved electronic logic circuits, a two-step simulation algorithm was proposed to reduce computation complexity of simulating circuits and to improve the simulation efficiency. At last, a random number generator was automatically designed with this encoding scheme and the proposed simulation algorithm, and the result showed this method was efficient.

[1]  Tatiana Kalganova,et al.  Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[2]  Peter J. Bentley,et al.  On Evolvable Hardware , 2001 .

[3]  Isamu Kajitani,et al.  Variable length chromosome GA for evolvable hardware , 1996, Proceedings of IEEE International Conference on Evolutionary Computation.

[4]  Jim Torresen,et al.  Evolving Multiplier Circuits by Training Set and Training Vector Partitioning , 2003, ICES.

[5]  Albert Y. Zomaya Handbook of Nature-Inspired and Innovative Computing - Integrating Classical Models with Emerging Technologies , 2006 .

[6]  Peter J. Bentley,et al.  Development brings scalability to hardware evolution , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[7]  Mehrdad Salami,et al.  Evolvable hardware at function level , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[8]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[9]  Kang Li EVOLVABLE HARDWARE REALIZED WITH FUNCTION TYPE PROGRAMMABLE DEVICE , 1999 .