Performance Figures of Non-Volatile Memories

The selection of one memory architecture during the system development process is based on an assessment of cost per bit, scalability, and power efficiency and performance values.

[1]  Ad J. van de Goor,et al.  Optimizing stresses for testing DRAM cell defects using electrical simulation , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Sivan Toledo,et al.  Algorithms and data structures for flash memories , 2005, CSUR.

[3]  Tony Givargis,et al.  Deterministic Service Guarantees for NAND Flash using Partial Block Cleaning , 2009 .

[4]  Luis A. Lastras,et al.  Write amplification reduction in NAND Flash through multi-write coding , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).