Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion

Modern Integrated circuits (ICs) suffer from excessive power and temperature issues because of embedding a large number of applications on small silicon real estate. Low power technique is introduced to reduce the power. With the reduction of power, area of circuit increases and vice versa. It shows a trade-off nature between them. Increase of area is against the trend of technology scaling which demands small area. Due to small area and high power dissipation, power-density increases. As power-density is directly converging into temperature, it emerges as a challenge in front of the VLSI design engineer to minimize the effect of temperature by reducing power-density. In this work, an attempt has been made to reduce the effect of powerdensity along with area and power so that AND-XOR based circuit is balanced in terms of area, power, and temperature. AND-XOR based reed-muller (RM) mixed polarity circuit forms are considered in this work. Polarity conversions are made in such a way that possibility of maximum sharing among the sub-function is increased. Genetic algorithm is (a non-exhaustive heuristic algorithm) used to select the polarity of the input variable for maximum sharing. The proposed synthesis approach shows 27.11%, 20.69%, and 32.30% savings in area, power, and power-density respectively than that of reported results. For the validation of the proposed approach, the best solutions are implemented in Cadence digital domain to obtain actual silicon area and power consumption. HotSpot tool is used to get the absolute temperature of the circuit.

[1]  Marek A. Perkowski,et al.  Fast minimization of mixed-polarity AND/XOR canonical networks , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[2]  Hafizur Rahaman,et al.  Testable design of AND-EXOR logic networks with universal test sets , 2009, Comput. Electr. Eng..

[3]  Jaskirat Singh,et al.  Two-Level Alloyed Branch Predictor based on Genetic Algorithm for Deep Pipelining Processors , 2017 .

[4]  Kaushik Roy,et al.  A graph-based synthesis algorithm for AND/XOR networks , 1997, DAC.

[5]  M. Yang,et al.  Optimization of mixed polarity reed-muller functions using genetic algorithm , 2011, 2011 3rd International Conference on Computer Research and Development.

[6]  Lingli Wang.  Automated synthesis and optimization of multilevel logic circuits. , 2000 .

[7]  Limin Xiao,et al.  A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions , 2017, Journal of Computer Science and Technology.

[8]  Sambhu Nath Pradhan,et al.  Thermal aware FPRM based AND-XOR network synthesis of logic circuits , 2015, 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS).

[9]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .

[10]  Tsutomu Sasao.  EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Limin Xiao,et al.  Power Optimization in Logic Synthesis for Mixed Polarity Reed-Muller Logic Circuits , 2015, Comput. J..

[12]  Santanu Chattopadhyay,et al.  Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach , 1996, IEEE Trans. Computers.

[13]  Irving S. Reed,et al.  A class of multiple-error-correcting codes and the decoding scheme , 1954, Trans. IRE Prof. Group Inf. Theory.

[14]  Sambhu Nath Pradhan,et al.  Thermal aware output polarity selection of programmable logic arrays , 2015, 2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV).

[15]  Marek A. Perkowski,et al.  Generalized Partially-Mixed-Polarity Reed-Muller Expansionand Its Fast Computation , 1996, IEEE Trans. Computers.

[16]  Tsutomu Sasao,et al.  Switching Theory for Logic Synthesis , 1999, Springer US.

[17]  Manu Sood,et al.  A Genetic Approach Based Solution for Seat Allocation during Counseling for Engineering Courses , 2016 .

[18]  Jean-Pierre Deschamps,et al.  Discrete and switching functions , 1978 .

[19]  Santanu Chattopadhyay,et al.  Fixed Polarity Reed-Muller Network Synthesis and Its Application in AND-OR/XOR-based Circuit Realization with Area-Power Trade-off , 2008 .

[20]  K VijayakumariC,et al.  A Simplified Efficient Technique for the Design of Combinational Logic Circuits , 2015 .

[21]  Sambhu Nath Pradhan,et al.  Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits , 2016, VLSI Design.

[22]  Li Hui,et al.  Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity , 2011 .

[23]  A. Das,et al.  An elitist area-power density trade-off in VLSI floorplan using genetic algorithm , 2012, 2012 7th International Conference on Electrical and Computer Engineering.

[24]  Shahin Nazarian,et al.  Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods , 2006, Proceedings of the IEEE.

[25]  Limin Xiao,et al.  Optimization of best polarity searching for mixed polarity reed-muller logic circuit , 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

[26]  Neil Urquhart,et al.  Manipulation and optimisation techniques for Boolean logic , 2010, IET Comput. Digit. Tech..

[27]  Limin Xiao,et al.  An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits , 2016, Frontiers of Computer Science.

[28]  Santanu Chattopadhyay,et al.  AND-XOR Network Synthesis with Area-Power Trade-off , 2008 .

[29]  Tsutomu Sasao,et al.  On the complexity of mod-2l sum PLA's , 1990 .

[30]  Hui Li,et al.  Area minimization of MPRM circuits , 2009, 2009 IEEE 8th International Conference on ASIC.

[31]  J. M. Saul.  Logic synthesis for arithmetic circuits using the Reed-Muller representation , 1992, [1992] Proceedings The European Conference on Design Automation.

[32]  Seok-Bum Ko,et al.  Efficient Realization of Parity Prediction Functions in FPGAs , 2004, J. Electron. Test..

[33]  Hamdy M. Mousa.  DNA-Genetic Encryption Technique , 2016 .