A New Hierarchical Simulator for Highly Parallel Analog Processor Arrays

System simulation, evaluation and analysis of highly parallel analog systems with conventional simulation tools is quite difficult due to their high complexity. Therefore we developed a methodology for the analysis of such systems by means of an applied simulation system. This approach bases on a relaxation method. The application of this technique accelerates the simulation of highly parallel analog systems by several orders of magnitude compared with standard circuit simulators. As additional feature, it can be traded-off between simulation expenditure and accuracy. We present the simulation method and its advantages in addition to a practical example.