Radix-8 division with over-redundant digit set

We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obtain simple digit selection rules. We show that the proposed enlarged set of values for the quotient digit does not lead to increases both in the complexity and the delay of the adder required to update the remainder, with respect to similar solutions, since the values allowed for the quotient digit have been selected carefully. The digit selection process is subdivided into two concurrent steps, each one making reference to a secondary digit set and the resulting implementation can be cheaper and faster than other units which do not use over-redundant digit sets. A performance analysis estimates a speed improvement from 25% to 35% with respect to a radix-8 architecture by Fandrianto, and from 21% to 30% with respect to a radix-4 architecture with prescaling, presented by Ercegovac and Lang. As required from the IEEE 754 floating point standard, the proposed algorithm features the correct remainder of the division.

[1]  Naofumi Takagi,et al.  Design of high speed MOS multiplier and divider using redundant binary representation , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[2]  Jan Fandrianto Algorithm for high speed shared radix 8 division and radix 8 square root , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[3]  Luigi Ciminiera,et al.  Over Redundant Digit Sets and the Design of Digit-by-Digit Division Units , 1994, IEEE Trans. Computers.

[4]  Damiel E. Atkins Higher-Radix Division Using Estimates of the Divisor and Partial Remainders , 1968, IEEE Transactions on Computers.

[5]  Tomás Lang,et al.  On-line scheme for computing rotation factors , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[6]  James E. Robertson,et al.  A New Class of Digital Division Methods , 1958, IRE Trans. Electron. Comput..

[7]  Shmuel Winograd,et al.  On the Time Required to Perform Addition , 1965, JACM.

[8]  J. B. Gosling,et al.  Design of a Hih-Speed Square Root Multiply and Divide Unit , 1987, IEEE Transactions on Computers.

[9]  Tomás Lang,et al.  Simple Radix-4 Division with Opterands Scaling , 1990, IEEE Trans. Computers.

[10]  Milos D. Ercegovac,et al.  A higher-radix division with simple selection of quotient digits , 1983, 1983 IEEE 6th Symposium on Computer Arithmetic (ARITH).

[11]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[12]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[13]  Mark Horowitz,et al.  SRT division diagrams and their usage in designing intergrated circuits for division , 1986 .

[14]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[15]  Robert Alverson,et al.  Integer division using reciprocals , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[16]  Tomás Lang,et al.  Fast Multiplication Without Carry-Propagate Addition , 1990, IEEE Trans. Computers.

[17]  Jan Fandrianto Algorithm for high speed shared radix 4 division and radix 4 square-root , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[18]  George S. Taylor Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[19]  Michael J. Flynn,et al.  Fast division using accurate quotient approximations to reduce the number of iterations , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[20]  Luigi Ciminiera,et al.  Algorithm and architectures for radix-4 division with over-redundant digit set and simple digit selection hardware , 1991, [1991] Conference Record of the Twenty-Fifth Asilomar Conference on Signals, Systems & Computers.

[21]  Erdem Hokenek,et al.  Design of the IBM RISC System/6000 Floating-Point Execution Unit , 1990, IBM J. Res. Dev..

[22]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Luigi Ciminiera,et al.  Design of a Radix 4 Division Unit with Simple Selection Table , 1992, IEEE Trans. Computers.

[24]  Tomás Lang,et al.  On-the-Fly Rounding , 1992, IEEE Trans. Computers.