Method for verifying error of digital circuit

Digital circuit error verification method according to an embodiment of the present invention, a digital circuit error verification device, the first digital circuit using the metadata of the design to produce a first property value, the first digital circuit digital design points performing a mechanical decomposition of a device unit with respect to the circuit, it generates a second attribute value by using the result of the mechanical decomposition, generate the attribute data base including the first attribute and second attribute values, the said digital circuit error verification device, the attribute performing supervised learning to generate the pattern corresponding to the verification object, using the data base, and wherein the step of generating comprising the resulting patterns pattern database, and said digital circuit error verification device are, the same analysis of the second digital circuit design verification subject to error as in the first digital circuit design 3 Property Value and fourth generate attribute values, and generate a verification request data including the same, and the pattern database, the comparison target pattern, and the verification request, the data comparator selecting the target pattern, and wherein the selection of the verification object in comparison can include the step of verifying the second error of the digital circuit design by.