A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.

[1]  Pierre-Emmanuel Gaillardon,et al.  A Taxonomy and Evaluation Framework for Memristive Logic , 2019, Handbook of Memristor Networks.

[2]  Hyunsang Hwang,et al.  Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory , 2016 .

[3]  Alessandro Manstretta,et al.  A new serial sensing approach for multistorage non-volatile memories , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[4]  Jeonghwan Song,et al.  Resistance controllability and variability improvement in a TaOx-based resistive memory for multilevel storage application , 2015 .

[5]  Cristian Zambelli,et al.  Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention , 2019, IEEE Journal of the Electron Devices Society.

[6]  Pierre-Emmanuel Gaillardon,et al.  Memristive logic: A framework for evaluation and comparison , 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[7]  Ameer Haj-Ali,et al.  mMPU—A Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck , 2020 .

[8]  Hyunsang Hwang,et al.  Multi-state resistance switching and variability analysis of HfOx based RRAM for ultra-high density memory applications , 2015, 2015 International Symposium on Next-Generation Electronics (ISNE).

[9]  Dietmar Fey,et al.  A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability , 2019, IEEE Transactions on Nanotechnology.

[10]  H.-S. Philip Wong,et al.  Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell , 2019, IEEE Transactions on Electron Devices.

[11]  John Reuben,et al.  Low power, high speed hybrid clock divider circuit , 2013, 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT).

[12]  Pinaki Mazumder,et al.  A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory , 2017, IEEE Transactions on Nanotechnology.

[13]  Meng-Fan Chang,et al.  Emerging NVM Circuit Techniques and Implementations for Energy-Efficient Systems , 2018, Beyond-CMOS Technologies for Next Generation Computer Design.

[14]  Hyunsang Hwang,et al.  Effect of Nitrogen Doping on Variability of TaOx -RRAM for Low-Power 3-Bit MLC Applications , 2015 .

[15]  Z. Wang,et al.  CMOS adjustable Schmitt triggers , 1991 .

[16]  Borivoje Nikolić,et al.  A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Harish M. Kittur,et al.  A novel clock generation algorithm for system-on-chip based on least common multiple , 2014, Comput. Electr. Eng..

[18]  Daniele Ielmini,et al.  Impact of oxide and electrode materials on the switching characteristics of oxide ReRAM devices. , 2019, Faraday discussions.

[19]  Hyunsang Hwang,et al.  Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering , 2015, IEEE Electron Device Letters.

[20]  Kiat Seng Yeo,et al.  Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler , 2006, IEEE Transactions on Microwave Theory and Techniques.