论文信息 - A 95 mW, 10 b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme

A 95 mW, 10 b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme

A very-low-power, 95 mW, 10 b 15 MHz CMOS pipelined fully differential A/D converter (ADC) is fabricated using analog double sampling. Excellent power reduction is achieved using this sampling technique and a 3.3 V supply voltage design for comparator circuits. The 5 V internal supply is generated by an on-chip 3.3 V to 5 V charge pumping voltage generator. The fully differential approach is compatible with this type of implementation. The amplifier has a triple cascode configuration to achieve a gain of 80 dB. The converter exhibits good performance at 15 MHz, very good input bandwidth of 7.53 MHz at the 15 MHz conversion rate, and good linearity. Excellent power dissipation is observed.<<ETX>>

Kunihiko Usui | Eiki Imaizumi | S. Ueda | T. Matsuura | M. Hotta

[1] S. H. Lewis,et al. A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[2] S.H. Lewis,et al. A pipelined 9-stage video-rate analog-to-digital converter , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[3] Masao Hotta,et al. A 10-bit 20-MHz two-step parallel A/D converter with internal S/H , 1989 .

[4] Eiji Takeda,et al. An experimental 1.5-V 64-Mb DRAM , 1991 .