Trends in Low-Power, Digitally Assisted A/D Conversion

This paper discusses recent trends in the area of low-power, high-performance A/D conversion. We examine survey data collected over the past twelve years to show that the conversion energy of ADCs has halved every two years, while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling, and developments in ADC design are then presented to explain the observed trends. Finally, we review opportunities in digitally assisted design for the most popular converter architectures.

[1]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Franz Kuttner,et al.  A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Sunghyun Park,et al.  A 4-GS/s 4-bit Flash ADC in 0.18- $\mu{\hbox {m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.

[4]  K. Teer,et al.  Bucket-brigade electronics: new possibilities for delay, time-axis conversion, and scanning , 1969 .

[5]  Robert H. Walden,et al.  Analog-to-digital converter survey and analysis , 1999, IEEE J. Sel. Areas Commun..

[6]  Boris Murmann,et al.  System embedded ADC calibration for OFDM receivers , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Boris Murmann,et al.  A/D converter trends: Power dissipation, scaling and digitally assisted architectures , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[8]  Y. Tamba,et al.  A CMOS 6 b 500 MSample/s ADC for a hard disk drive read channel , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[9]  Kenneth W. Martin,et al.  A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Geert Van der Plas,et al.  A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[11]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[12]  Maarten Vertregt,et al.  Systematic power reduction and performance analysis of mismatch limited ADC designs , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[13]  H. Matsui,et al.  A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration , 2006, IEEE Journal of Solid-State Circuits.

[14]  Ya-Lun Yang,et al.  A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[15]  B.P. Ginsburg,et al.  Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[16]  Youngcheol Chae,et al.  Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator , 2009, IEEE Journal of Solid-State Circuits.

[17]  Borivoje Nikolic,et al.  Least mean square adaptive digital background calibration of pipelined analog-to-digital converters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  Shoji Kawahito,et al.  Low-Power Design of Pipeline A/D Converters , 2006, IEEE Custom Integrated Circuits Conference 2006.

[19]  L. Kushner,et al.  A process-scalable low-power charge-domain 13-bit pipeline ADC , 2008, 2008 IEEE Symposium on VLSI Circuits.

[20]  B. Murmann,et al.  A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification , 2009, IEEE Journal of Solid-State Circuits.

[21]  Stephen H. Lewis,et al.  Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Boris Murmann,et al.  A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[23]  A.A. Abidi,et al.  The Path to the Software-Defined Radio Receiver , 2007, IEEE Journal of Solid-State Circuits.

[24]  David A. Johns,et al.  A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[25]  Jan Craninckx,et al.  A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS , 2010, IEEE Journal of Solid-State Circuits.

[26]  B. Razavi,et al.  A 10-Bit 500-MS/s 55-mW CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[27]  Y. Chiu High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS , 2004 .

[28]  Klaas Bult,et al.  The Effect of Technology Scaling on Power Dissipation in Analog Circuits , 2006 .

[29]  Hae-Seung Lee,et al.  Comparator-based switched-capacitor circuits for scaled CMOS technologies , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[30]  S. Devarajan,et al.  A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC , 2009, IEEE Journal of Solid-State Circuits.

[31]  Krishnamurthy Soumyanath,et al.  A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[32]  Stephen H. Lewis,et al.  Digital background calibration for memory effects in pipelined analog-to-digital converters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  G. Van der Plas,et al.  A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[34]  Yuji Nakajima,et al.  A self-background calibrated 6b 2.7GS/s ADC with cascade-calibrated folding-interpolating architecture , 2009, 2009 Symposium on VLSI Circuits.

[35]  T. Toifl,et al.  A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[36]  L. R. Carley,et al.  An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC , 1995 .

[37]  P.J. Hurst,et al.  A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration , 2004, IEEE Journal of Solid-State Circuits.

[38]  Boris Murmann,et al.  Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs , 2007, IEEE Transactions on Instrumentation and Measurement.

[39]  Patrick Satarzadeh,et al.  Digital Calibration of a Nonlinear S/H , 2009, IEEE Journal of Selected Topics in Signal Processing.

[40]  S. Ramprasad,et al.  A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[41]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[42]  A. Montijo,et al.  A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[43]  Klaas Bult Embedded analog-to-digital converters , 2009, 2009 Proceedings of ESSCIRC.

[44]  Luc Astier,et al.  Power consumption of A/D converters for software radio applications , 2000, IEEE Trans. Veh. Technol..

[45]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[46]  Geert Van der Plas,et al.  A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS , 2008, IEEE Journal of Solid-State Circuits.

[47]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.

[48]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[49]  Borivoje Nikolic,et al.  Scaling of analog-to-digital converters into ultra-deep-submicron CMOS , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[50]  K. G. Merkel,et al.  A survey of high performance analog-to-digital converters for defense space applications , 2003, 2003 IEEE Aerospace Conference Proceedings (Cat. No.03TH8652).

[51]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[52]  Jan Craninckx,et al.  A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[53]  R. van Langevelde,et al.  Designing outside rail constraints , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[54]  Shoji Kawahito,et al.  A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[55]  Paul Voois,et al.  A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s , 2008, IEEE Journal of Solid-State Circuits.

[56]  Chun-Cheng Huang,et al.  A background comparator calibration technique for flash analog-to-digital converters , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[57]  Robert H. M. van Veldhoven,et al.  An Inverter-Based Hybrid ΔΣ Modulator , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[58]  Eric A. Vittoz,et al.  Future of analog in the VLSI environment , 1990, IEEE International Symposium on Circuits and Systems.

[59]  Un-Ku Moon,et al.  Background calibration techniques for multistage pipelined ADCs with digital redundancy , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[60]  Won Namgoong,et al.  A channelized digital ultrawideband receiver , 2003, IEEE Trans. Wirel. Commun..

[61]  Upamanyu Madhow,et al.  Joint Channel and Mismatch Correction for OFDM Reception with Time-interleaved ADCs: Towards Mostly Digital MultiGigabit Transceiver Architectures , 2008, IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference.

[62]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[63]  Eric Andre,et al.  A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[64]  Matthias Frey,et al.  On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[65]  Tetsuya Matsumoto,et al.  A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture , 2010, IEEE Journal of Solid-State Circuits.

[66]  E. Alon,et al.  Replica compensated linear regulators for supply-regulated phase-locked loops , 2006, IEEE Journal of Solid-State Circuits.

[67]  Boris Murmann,et al.  Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[68]  Kenneth W. Martin,et al.  A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[69]  Christian Vogel,et al.  A Flexible and Scalable Structure to Compensate Frequency Response Mismatches in Time-Interleaved ADCs , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[70]  George Chien,et al.  High-speed, Low-power, Low Voltage Pipelined Analog-to-digital Converter High Speed, Low Power, Low Voltage Pipelined Analog-to-digital Converter Chapter 1 Introduction Chapter 4 Experimenta Prototype and Measurement Results Appendix a Reference Voltage Generator , 1996 .

[71]  G. Chien,et al.  A power-optimized CMOS baseband channel filter and ADC for cordless applications , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[72]  Soon-Jyh Chang,et al.  A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process , 2009, 2009 Symposium on VLSI Circuits.

[73]  Boris Murmann,et al.  LIMITS ON ADC POWER DISSIPATION , 2006 .

[74]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[75]  Håkan Johansson,et al.  Time-interleaved analog-to-digital converters: status and future directions , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[76]  Keith Anthony O'Donoghue Digital calibration of a switched-capacitor delta-sigma analog -to -digital converter , 2009 .

[77]  Behzad Razavi,et al.  A 12-Bit 200-MHz CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[78]  P.J. Hurst,et al.  A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[79]  Boris Murmann,et al.  Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters , 2009, IEEE Journal of Selected Topics in Signal Processing.

[80]  D. Draxelmayr,et al.  A 6b 600MHz 10mW ADC array in digital 90nm CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[81]  Jan Craninckx,et al.  A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[82]  Fredrik Gustafsson,et al.  Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.