Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads

When using dynamically and partially reconfigurable FPGAs in embedded systems, the scheduler needs to fulfill area and time requirements for each task. While those demands are already well studied in literature, another characteristic peculiarity of reconfigurable systems has been rather neglected: the reconfiguration overhead. However, scheduling algorithms considering the exclusive access to the reconfiguration port can improve the latency of obtained schedules considerably. In this paper, we present new scheduling heuristics and a methodology to compare approaches which take into consideration the reconfiguration overheads with those which disregard them. Furthermore, our experimental results give insight into possible performance increases and present problem instances for which the reconfiguration latency is negligible.

[1]  Andrew Wirth,et al.  Equal processing and equal setup time cases of scheduling parallel machines with a single server , 2004, Comput. Oper. Res..

[2]  Peter Brucker,et al.  Complexity results for parallel machine problems with a single server , 2002 .

[3]  V. Tanaev,et al.  Scheduling theory single-stage systems , 1994 .

[4]  Jürgen Teich,et al.  The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[5]  E.L. Lawler,et al.  Optimization and Approximation in Deterministic Sequencing and Scheduling: a Survey , 1977 .

[6]  Sándor P. Fekete,et al.  Scheduling and CommunicationüAware Mapping of HW/SW Modules for Dynamically and Partially Reconfigurable SoC Architectures , 2007 .

[7]  Javier Resano,et al.  Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware , 2004, Proceedings. 41st Design Automation Conference, 2004..

[8]  Jürgen Teich,et al.  The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer , 2007, J. VLSI Signal Process..

[9]  Svetlana A. Kravchenko,et al.  Parallel machine scheduling problems with a single server , 1997 .

[10]  Nikil D. Dutt,et al.  Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[11]  Andrew Wirth,et al.  Scheduling parallel machines with a single server: some solvable cases and heuristics , 2002, Comput. Oper. Res..

[12]  Dorit S. Hochba,et al.  Approximation Algorithms for NP-Hard Problems , 1997, SIGA.

[13]  Marco Platzner,et al.  A Runtime Environment for Reconfigurable Hardware Operating Systems , 2004, FPL.

[14]  Jürgen Teich,et al.  Optimal FPGA module placement with temporal precedence constraints , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[15]  Heiko Kalte,et al.  Task placement for heterogeneous reconfigurable architectures , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[16]  D. Atkin.  OR scheduling algorithms. , 2000, Anesthesiology.

[17]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[18]  Florian Dittmann,et al.  Hard Real-Time Reconfiguration Port Scheduling , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Chelliah Sriskandarajah,et al.  Parallel machine scheduling with a common server , 2000, Discret. Appl. Math..