A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations of a clock distribution network using the proposed driver shows a 66%-76% reduction in 3sigma clock skew value and 84%-88% reduction in clock tree delay compared to using conventional drivers. A 0.4-V test chip has been fabricated in a 0.18-mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations.

[1]  N. Tzartzanis,et al.  Differential current-mode sensing for efficient on-chip global signaling , 2005, IEEE Journal of Solid-State Circuits.

[2]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[3]  Anantha P. Chandrakasan,et al.  Subthreshold Circuit Techniques , 2004 .

[4]  David Blaauw,et al.  Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[5]  S. Naffziger,et al.  Statistical clock skew modeling with data delay variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[6]  B. Calhoun,et al.  Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  K. Yamashita,et al.  Interconnect scaling scenario using a chip level interconnect model , 2000 .

[8]  X. Dai.  An adaptive digital deskewing circuit for clock distribution networks , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[9]  M. Shoji,et al.  Elimination of process-dependent clock skew in CMOS VLSI , 1986 .

[10]  Mark A. Franklin,et al.  Optimum buffer circuits for driving long uniform lines , 1991 .

[11]  G. Patounakis,et al.  Pulsed current-mode signaling for nearly speed-of-light intrachip communication , 2006, IEEE Journal of Solid-State Circuits.

[12]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[13]  R. Bashirullah,et al.  A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[14]  J. B. Kuo,et al.  A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI , 1997 .

[15]  G.A. Rigby,et al.  A 1V bootstrapped CMOS digital logic family , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[16]  Dennis Sylvester,et al.  Interconnect scaling: signal integrity and performance in future high-speed CMOS designs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[17]  James B. Kuo,et al.  Ultra-low-voltage SOI CMOS inverting driver circuit using effective charge pump based on bootstrap technique , 2003 .

[18]  Jason Liu,et al.  A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  M. Khellah,et al.  Static pulsed bus for on-chip interconnects , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[20]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[21]  Kaushik Roy,et al.  Ultra-low power DLMS adaptive filter for hearing aid applications , 2001, ISLPED '01.