Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.

[1]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[2]  Chengkuo Lee,et al.  A Junctionless Gate-All-Around Silicon Nanowire FET of High Linearity and Its Potential Applications , 2013, IEEE Electron Device Letters.

[3]  Ran Yan,et al.  Junctionless Multiple-Gate Transistors for Analog Applications , 2011, IEEE Transactions on Electron Devices.

[4]  Sylvain Barraud,et al.  Low-temperature electrical characterization of junctionless transistors , 2013 .

[5]  Bulusu Anand,et al.  Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic , 2014, IEEE Transactions on Nanotechnology.

[6]  Guo-Qiang Lo,et al.  Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire , 2011, IEEE Electron Device Letters.

[7]  Subhasis Haldar,et al.  Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor , 2015, IEEE Transactions on Electron Devices.

[8]  A. Vandooren,et al.  CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET) , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[9]  Chi-Woo Lee,et al.  High-Temperature Performance of Silicon Junctionless MOSFETs , 2010, IEEE Transactions on Electron Devices.

[10]  G. A. Armstrong,et al.  High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications , 2012, IEEE Electron Device Letters.

[11]  Kartik Mohanram,et al.  Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Ali Rostami,et al.  A Dual-Color IR Quantum Cascade Photodetector With Two Output Electrical Signals , 2011, IEEE Transactions on Electron Devices.

[13]  J.G. Fossum,et al.  Multiple independent gate field effect transistor (MIGFET) - multi-fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[14]  Yiqi Zhuang,et al.  Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs , 2013, IEEE Transactions on Electron Devices.

[15]  Sung-Jin Choi,et al.  Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors , 2011, IEEE Electron Device Letters.

[16]  Tsu-Jae King Liu,et al.  Design of Gate-All-Around Silicon MOSFETs for 6-T SRAM Area Efficiency and Yield , 2014, IEEE Transactions on Electron Devices.

[17]  Te-Kuang Chiang,et al.  A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges , 2011, IEEE Transactions on Electron Devices.

[18]  H.-S. Philip Wong,et al.  Beyond the Conventional MOSFET , 2001 .

[19]  Sung-Jin Choi,et al.  Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate , 2013, IEEE Transactions on Electron Devices.

[20]  V. Kumari,et al.  Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket , 2012, IEEE Transactions on Electron Devices.

[21]  Subhasis Haldar,et al.  An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering , 2014, Microelectron. J..

[22]  Subhasis Haldar,et al.  Performance Evaluation and Reliability Issues of Junctionless CSG MOSFET for RFIC Design , 2014, IEEE Transactions on Device and Materials Reliability.

[23]  Hiroshi Iwai,et al.  CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET , 2014, IEEE Transactions on Electron Devices.

[24]  Abhinav Kranti,et al.  Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion , 2011 .

[25]  Giovanni De Micheli,et al.  Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[26]  Zhuang Yiqi,et al.  New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs , 2011 .