Stress analysis of a standard CMOS process

Thin film stress has turned out to be a limiting factor for the fabrication of dielectric membrane based microsystem using commercial CMOS processes. Due to the compressive stress in the CMOS dielectrics, membranes tend to buckle and - in the extreme case - to break, i.e., the sensor yield is reduced and consequently production costs rise. In this paper we report the results of the stress analysis of a commercial 1 micrometers , single poly, double metal CMOS process. All dielectric layers from the field oxide to the passivation were analyzed. We investigate several methods to taylor the stresses in the dielectrics to the needs of microsensor fabrication. The most mature method was to change the stress in the passivation layer by adjusting the deposition parameters. We investigated two passivation layers in more detail. With the standard passivation the dielectric sandwich has a total thickness of nearly 4 micrometers and an average stress of -162 MPa. The second passivation layer is thicker and more tensile than the standard passivation. It reduces the average stress to -15 MPa. The critical buckling lengths of CMOS dielectric membranes were determined experimentally. We found the critical buckling lengths of such membranes containing these two passivation layers to be (194 + 26) micrometers and (967 + 103) micrometers , respectively.