A 15 b 5 MSample/s low-spurious CMOS ADC

This 15b CMOS ADC at 5MSample/s has four stages with 5, 5, 5, and 6b each. The number of bits resolved per stage is set higher to achieve the same resolution with less accurate components. Resolving more bits per stage greatly simplifies op amp design and reduces the initial capacitor matching requirement. Furthermore, residue amplifiers with low feedback factors are less sensitive to summing-node parasitics. The first two 5b stages are calibrated using the remaining part of the ADC. Two stages are selected for calibration. The gain ofthe 5b residue amplifier is set to 16 to make room for digital correction. After digital correction, the chip has an 18b output. Performance up to 16b level can be tested after removing 2 LSBs corrupted by digital processing. System partitioning and multi-stage calibration solve two fundamental problems of capacitor matching and finite opamp gain.

[1]  Bang-Sup Song,et al.  A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .

[2]  Donald A. Kerth,et al.  A 12-bit, 1-MHz, two-step flash ADC , 1989 .

[3]  M. F. Tompsett,et al.  A 10-b 15-MHz CMOS recycling two-step A/D converter , 1990 .

[4]  Paul R. Gray,et al.  A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS , 1991 .

[5]  Bang-Sup Song,et al.  Digital-domain calibration of multistep analog-to-digital converters , 1992 .

[6]  Behzad Razavi,et al.  A 12-b 5-Msample/s two-step CMOS A/D converter , 1992 .

[7]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[8]  Bang-Sup Song,et al.  Interstage gain proration technique for digital-domain multi-step ADC calibration , 1994 .

[9]  Frank Murden,et al.  12b 50MSample/s two-stage A/D converter , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[10]  Bang-Sup Song,et al.  A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter , 1995, IEEE J. Solid State Circuits.

[11]  Bang-Sup Song,et al.  A 10-b 20-Msample/s low-power CMOS ADC , 1995, IEEE J. Solid State Circuits.

[12]  Paul R. Gray,et al.  A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 /spl mu/m CMOS , 1996 .

[13]  L. Singer,et al.  A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[14]  Hae-Seung Lee,et al.  A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[15]  M. K. Mayes,et al.  A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller , 1996 .

[16]  Shin-Il Lim,et al.  A 12 b 10 MHz 250 mW CMOS A/D converter , 1996 .

[17]  Un-Ku Moon,et al.  Background digital calibration techniques for pipelined ADCs , 1997 .

[18]  J. Doernberg,et al.  A 12 b 128 MSample/s ADC with 0.05 LSB DNL , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.