State machine description oriented towards effective usage of vendor-independent synthesis tools

Abstract The paper concerns the problem of Finite State Machine (FSM) description in Hardware Description Languages (HDL), and effective usage of vendor-independent synthesis tools, including academic software, in synthesis dedicated for Complex Programmable Logic Devices (CPLD-s). The authors propose an alternative method of porting a design from a vendor-independent synthesis tool to a vendor system, for completing the implementation stage. The method utilises a special style of VHDL modelling, so the description is universal and comprehendible to a human. Efficiency of the method was verified by experiments carried out using academic software, and leading commercial tools.

[1]  Dariusz Kania.  Logic synthesis of multi-output functions for PAL-based CPLDs , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[2]  Dariusz Kania,et al.  State assignment for PAL-based CPLDs , 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

[3]  Gabriele Saucier,et al.  Multi-level synthesis on PALs , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[4]  Robert Czerwinski,et al.  FSMs state encoding targeting at logic level minimization , 2006 .

[5]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.