Large integrated crossbar switch

This paper describes the design of a 256/spl times/256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant monolithic implementation in a 0.8 micron CMOS technology. The number of spare rows and columns in the switch matrix was determined by a detailed yield analysis.

[1]  Cüneyt M. Özveren,et al.  GIGAswitch System: A High-performance Packet-switching Platform , 1994, Digit. Tech. J..

[2]  Joydeep Ghosh,et al.  Reduction of simultaneous-switching noise in large crossbar networks , 1991 .

[3]  N. Mirfakhraei.  Wafer-scale integration as a technology choice for high speed ATM switching systems , 1994, Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI).

[4]  Douglas A. Pucknell,et al.  BASIC VLSI DESIGN: Systems and Circuits. , 1988 .

[5]  Joseph Di Giacomo.  Digital bus handbook , 1990 .

[6]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[8]  Randall L. Geiger,et al.  VLSI Design Techniques for Analog and Digital Circuits , 1989 .

[9]  Wojciech Maly,et al.  Circuit design for a large area high-performance crossbar switch , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[10]  Thomas E. Dillinger.  VLSI Engineering , 1984, Lecture Notes in Computer Science.

[11]  Andreas G. Andreou,et al.  On fault probabilities and yield models for analog VLSI neural networks , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[12]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .