A 4-path 60GHz CMOS phased-array receiver

The 60-GHz worldwide unlicensed band provides up to 9-GHz bandwidth and thus enables Gb/s-data-rate point-to-point communication links and high-definition video transfer. However, implementations of circuits and systems at this frequency range are still quite challenging. This dissertation is dedicated to the design and demonstration of a high-performance 4-path 60-GHz phased-array receiver front-end (RFE) in CMOS technology with novel ideas at both system architecture and circuit implementation. At the circuit level, several novel design techniques for the key building blocks were demonstrated. First, a 24-GHz and 60-GHz dual-band standing-wave VCO with mode-switching technique was designed in 0.13μm CMOS process. Second, a bimodal transformer-based enhanced magnetic tuning technique was proposed to implement a quadrature VCO (QVCO) in 65nm CMOS process with an ultra-wide frequency tuning range from 48.8 GHz to 62.3 GHz (corresponding to 24 % tuning range at 60GHz) and figure-of-merit (FoM) of 181 to 184 dBc. Third, to operate the QVCO in a phased-lock loop (PLL), a harmonic-boosting technique with 4 th -order LC tank was proposed to achieve a divide-by-4 injection-locked frequency divider with state-of-the-art frequency

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