Integrated submicron switching transistor breaking the Si limit at 100 V

This paper reports on the record performance of a novel power switching device, integrated in a 0.35 μm based smart power technology. The transistor uses trench processing to make a vertical stack of gate oxide and drift oxide, the latter being used to completely deplete the drift region. The vertical gate oxide is 10 nm thick, allowing driving the gate with the low voltage CMOS supply. A very high cell density is obtained, leading to a specific on-resistance RON of 41 mΩ.mm2 for a reverse blocking voltage Vbd of 93 V, breaking the silicon limit. The sensitivity of RON and Vbd on the most important process parameters is highlighted.