28V ESD clamp in CMOS 40nm process

The thin gate oxide in nanoscale CMOS technologies is a serious challenge to the electrostatic discharge (ESD) robustness of ICs. This paper describes a sophisticated design solution for a 28V ESD clamp integrated in a 40nm CMOS product using only 2.75V transistors. It is suitable for I/O interface in SoC chips for mobile application and allows a battery charger to be connected directly to the chip. The presented clamp passed ESD/Latch-up test for HBM 3KV, 30V over-voltage test and 1000-hours prolonged operation life-time test.

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