A methodology for the early exploration of design rules for multiple-patterning technologies
暂无分享,去创建一个
[1] D. Marquardt. An Algorithm for Least-Squares Estimation of Nonlinear Parameters , 1963 .
[2] Kenneth Levenberg. A METHOD FOR THE SOLUTION OF CERTAIN NON – LINEAR PROBLEMS IN LEAST SQUARES , 1944 .
[3] Sachin S. Sapatnekar,et al. A predictive distributed congestion metric with application to technology mapping , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Lars W. Liebmann,et al. Decomposition-aware standard cell design flows to enable double-patterning technology , 2011, Advanced Lithography.
[5] Arvind Srinivasan,et al. RITUAL: a performance driven placement algorithm for small cell ICs , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[6] Yao-Wen Chang,et al. Native-conflict-aware wire perturbation for double patterning technology , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[7] J. Soukup. Circuit layout , 1981, Proceedings of the IEEE.
[8] Sani R. Nassif,et al. Simultaneous Layout Migration and Decomposition for Double Patterning Technology , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Daniel Roviras,et al. Levenberg-Marquardt learning neural network for adaptive predistortion for time-varying HPA with memory in OFDM systems , 2008, 2008 16th European Signal Processing Conference.
[10] Keith Phalp,et al. An investigation of machine learning based prediction systems , 2000, J. Syst. Softw..
[11] Yunfei Deng,et al. DPT restricted design rules for advanced logic applications , 2011, Advanced Lithography.
[12] Yunfei Deng,et al. Double patterning compliant logic design , 2011, Advanced Lithography.
[13] Feng Zhou,et al. Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction , 2002, SLIP '02.
[14] Andrew B. Kahng,et al. Accurate pseudo-constructive wirelength and congestion estimation , 2003, SLIP '03.
[15] A. H. Chao,et al. Direct solution of performance constraints during placement , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.
[16] Patrick Groeneveld,et al. Probabilistic congestion prediction , 2004, ISPD '04.
[17] Puneet Gupta,et al. A framework for double patterning-enabled design , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[18] Puneet Gupta,et al. A framework for early and systematic evaluation of design rules , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[19] Kun Yuan,et al. WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[20] Shankar Krishnamoorthy,et al. Estimating routing congestion using probabilistic analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] Sachin S. Sapatnekar,et al. Probabilistic Congestion Prediction with Partial Blockages , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).
[22] Malgorzata Marek-Sadowska,et al. Pre-layout wire length and congestion estimation , 2004, Proceedings. 41st Design Automation Conference, 2004..
[23] Chris C. N. Chu,et al. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.