PASS: a package for automatic scheduling and sharing pipelined data paths

A system for automatic scheduling and sharing data paths has been developed. It is generic; different design styles such as pipeline, chaining, loop pipelines, etc., have been considered, and solutions of fastest possible, cheapest possible, fastest within hardware constraints, or lowest cost within time constraint could be found according to the user's request. The entire design space then could be explored with it. The scheduling algorithm is stepwise selective dealing with hardware urgency, time urgency, interconnection urgency, data urgency, and control urgency in a serial method with multiple levels of selections. The concept of the sharing algorithm is to consider the inter-influenced properties between operator-sharing and register-sharing, construct two inter-involved sharing criteria for them simultaneously, and then merge them concurrently.<<ETX>>

[1]  Daniel P. Siewiorek,et al.  Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Fadi J. Kurdahi,et al.  REAL: A Program for REgister ALlocation , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Joos Vandewalle,et al.  Loop Optimization in Register-Transfer Scheduling for DSP-Systems , 1989, 26th ACM/IEEE Design Automation Conference.

[4]  Miodrag Potkonjak,et al.  A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs , 1989, 26th ACM/IEEE Design Automation Conference.

[5]  Nohbyung Park,et al.  SEHWA: A Program for Synthesis of Pipelines , 1986, 23rd ACM/IEEE Design Automation Conference.

[6]  Albert E. Casavant,et al.  Scheduling and hardware sharing in pipelined data paths , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[7]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Pierre G. Paulin,et al.  Scheduling and Binding Algorithms for High-Level Synthesis , 1989, 26th ACM/IEEE Design Automation Conference.

[9]  Barry M. Pangrle Splicer: a heuristic approach to connectivity binding , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[10]  Arun K. Majumdar,et al.  Allocation of multiport memories in data path synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  E. F. Girczyc,et al.  HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.