Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance when the code length is moderate. Check node processing is a bottleneck of the NB-LDPC decoding. In this paper, a novel half-row modified two-extra-column trellis min-max (HR-mTEC-TMM) algorithm is proposed for the check node processing to reduce not only the complexity but also the storage memory. The check node unit (CNU) architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed CNU architecture obtains a reduction of 28.3% for the area and 43.87% for the storage memory with an acceptable error-correcting performance loss, compared to existing work.

[1]  Dan Feng Zhao,et al.  Min-Max decoding for non binary LDPC codes , 2016 .

[2]  David Declercq,et al.  Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  D. Mackay,et al.  Low density parity check codes over GF(q) , 1998, 1998 Information Theory Workshop (Cat. No.98EX131).

[4]  Zhongfeng Wang,et al.  Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Hanho Lee,et al.  Two-Extra-Column Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  David Declercq,et al.  Decoding Algorithms for Nonbinary LDPC Codes Over GF$(q)$ , 2007, IEEE Transactions on Communications.

[7]  Xinmiao Zhang,et al.  Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Huyen Thi Pham,et al.  High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes , 2017, Integr..

[9]  David Declercq,et al.  Low latency T-EMS decoder for non-binary LDPC codes , 2013, 2013 Asilomar Conference on Signals, Systems and Computers.

[10]  Javier Valls-Coquillat,et al.  Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Javier Valls-Coquillat,et al.  Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Javier Valls-Coquillat,et al.  High-Performance NB-LDPC Decoder With Reduction of Message Exchange , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.