论文信息 - A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delay

A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delay

A 1-V 2.5-GHz double-rate phase-locked loop (PLL) with zero clock skew fabricated in a 0.18-/spl mu/m standard CMOS technology is presented. A novel phase-alignment technique is proposed to achieve an inherent zero delay between the input reference and the output. Operated with the input and output frequencies of 1.25 GHz and 2.50 GHz, respectively, and with a 1-V supply voltage, the PLL prototype measures a rms jitter of 1.3 ps and a peak-to-peak jitter of 8.1 ps while consuming 13 mW and occupying a chip area of 2.5 mm/sup 2/.

H.C. Luong | G.C.T. Leung

[1] A. Waizman. A delay line loop for frequency synthesis of de-skewed clock , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[2] Torsten Lehmann,et al. 1-V power supply CMOS cascode amplifier , 2001 .

[3] HongMo Wang. A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 /spl mu/m CMOS , 2000 .

[4] Takanori Saeki,et al. A direct-skew-detect synchronous mirror delay for application-specific integrated circuits , 1999 .

[5] David J. Foley,et al. CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator , 2001 .

[6] Ting-Ping Liu,et al. A 6.5 GHz monolithic CMOS voltage-controlled oscillator , 1999 .

[7] David J. Foley,et al. CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).