Verification environment for PCI target and Wishbone master interface module using system verilog

As the complexity of design of chip is increased in last decade, designers were not able to manage to design and verify the functionality of design. So the verification of chip as a separate field progressed in the last decade. In this project intention is to verify functionality of PCI (Peripheral Component Interconnect) target and Wishbone master interface module as per the specifications of PCI and Wishbone protocol supported by this chip. The purpose to choose this design is PCI is board level bus and Wishbone is chip level bus so the application of bridge circuit will be there in every system which consist PCI (which almost every PC (Personal Computer) has) and wishbone bus at chip level. Verification of both of the protocol is always a challenge. In given RTL design there is a chip which mimic as PCI slave for PCI master and as Wishbone master for Wishbone slave. So to verify its functionality one has to make environment which can generate / sense signals which are going or coming from / to the given bridge which is our DUV (Design Under Verification). In this paper environment is generated in System Verilog language.