On the Design of Approximate Restoring Dividers for Error-Tolerant Applications

This paper proposes several designs of approximate restoring dividers; two different levels of approximation (cell and array levels) are employed. Three approximate subtractor cells are utilized for integer subtraction as basic step of division; these cells tend to mitigate accuracy in subtraction with other metrics, such as circuit complexity and power dissipation. At array level, exact cells are either replaced or truncated in the approximate divider designs. A comprehensive evaluation of approximation at both cell- and array (divider) levels is pursued using error analysis and HSPICE simulation; different circuit metrics including complexity and power dissipation are evaluated. Different applications are investigated by utilizing the proposed approximate arithmetic circuits. The simulation results show that with extensive savings for power dissipation and circuit complexity, the proposed designs offer better error tolerant capabilities for quotient oriented applications (image processing) than remainder oriented application (modulo operations). The proposed approximate restoring divider is significantly better than the approximate non-restoring scheme presented in the technical literature.

[1]  Kaushik Roy,et al.  IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[2]  Magdy A. Bayoumi,et al.  A 10-transistor low-power high-speed full adder cell , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[3]  Fabrizio Lombardi,et al.  Approximate XOR/XNOR-based adders for inexact computing , 2013, 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013).

[4]  Shih-Lien Lu Speeding Up Processing with Approximation Circuits , 2004, Computer.

[5]  Fabrizio Lombardi,et al.  New Metrics for the Reliability of Approximate and Probabilistic Adders , 2013, IEEE Transactions on Computers.

[6]  Gang Wang,et al.  Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.

[7]  Peter J. Varman,et al.  High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Fabrizio Lombardi,et al.  Design and Analysis of Approximate Compressors for Multiplication , 2015, IEEE Transactions on Computers.

[9]  Puneet Gupta,et al.  Trading Accuracy for Power with an Underdesigned Multiplier Architecture , 2011, 2011 24th Internatioal Conference on VLSI Design.

[10]  Paolo Ienne,et al.  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.

[11]  Andrew B. Kahng,et al.  Accuracy-configurable adder for approximate arithmetic designs , 2012, DAC Design Automation Conference 2012.

[12]  Yin-Tsung Hwang,et al.  A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Shubhajit Roy Chowdhury,et al.  A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates , 2008 .

[14]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[15]  Kiat Seng Yeo,et al.  Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications , 2011, 2011 International SoC Design Conference.

[16]  Zhi-Hui Kong,et al.  Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Fabrizio Lombardi,et al.  Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing , 2015, ACM Great Lakes Symposium on VLSI.

[18]  Kiat Seng Yeo,et al.  Low-power high-speed multiplier for error-tolerant application , 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).