Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers

Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage <formula formulatype="inline"><tex Notation="TeX">$Q$</tex></formula>-band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 <formula formulatype="inline"> <tex Notation="TeX">$\mu$</tex></formula>m<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex></formula>500 <formula formulatype="inline"> <tex Notation="TeX">$\mu$</tex></formula>m including pads.

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