Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs

3D NAND flash memory exhibits two contrasting process characteristics from its manufacturing process. While process variability between different horizontal layers are well known, little has been systematically investigated about strong process similarity (PS) within the horizontal layer. In this paper, based on an extensive characterization study using real 3D flash chips, we show that 3D NAND flash memory possesses very strong process similarity within a 3D flash block: the word lines (WLs) on the same horizontal layer of the 3D flash block exhibit virtually equivalent reliability characteristics. This strong process similarity, which was not previously utilized, opens simple but effective new optimization opportunities for 3D flash memory. In this paper, we focus on exploiting the process similarity for improving the I/O latency. By carefully reusing various flash operating parameters monitored from accessing the leading WL, the remaining WLs on the same horizontal layer can be quickly accessed, avoiding unnecessary redundant steps for subsequent program and read operations. We also propose a new program sequence, called mixed order scheme (MOS), for 3D NAND flash memory which can further reduce the program latency. We have implemented a PS-aware FTL, called cubeFTL, which takes advantage of the proposed techniques. Our evaluation results show that cubeFTL can improve the IOPS by up to 48% over an existing PS-unaware FTL.

[1]  Donggun Park,et al.  Data retention characteristics of sub-100 nm NAND flash memory cells , 2003 .

[2]  Dae-Seok Byeon,et al.  A world's first product of three-dimensional vertical NAND Flash memory and beyond , 2014, 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS).

[3]  Chong Leong Gan,et al.  3D Flash Memories , 2016, Microelectron. Reliab..

[4]  Dong Woo Kim,et al.  Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.

[5]  A. Azzouz 2011 , 2020, City.

[6]  Onur Mutlu,et al.  Data retention in MLC NAND flash memory: Characterization, optimization, and recovery , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[7]  C. Hu,et al.  Random telegraph noise in flash memories - model and technology scaling , 2007, 2007 IEEE International Electron Devices Meeting.

[8]  Y. Iwata,et al.  Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[9]  Onur Mutlu,et al.  Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives , 2017, Proceedings of the IEEE.

[10]  Ying Yu,et al.  11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[11]  Y. Iwata,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[12]  Onur Mutlu,et al.  Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Kuo-Pin Chang,et al.  Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash , 2010, 2010 International Electron Devices Meeting.

[14]  Erez Zadok,et al.  Filebench: A Flexible Framework for File System Benchmarking , 2016, login Usenix Mag..

[15]  Zhang Xiaohua,et al.  A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology , 2017 .

[16]  Kinam Kim,et al.  Scalable Wordline Shielding Scheme using Dummy Cell beyond 40 nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell , 2006 .

[17]  Onur Mutlu,et al.  Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation , 2013, ICCD.

[18]  Wei Wu,et al.  Optimizing NAND flash-based SSDs via retention relaxation , 2012, FAST.

[19]  Kinam Kim,et al.  Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node , 2006, 2006 International Electron Devices Meeting.

[20]  Florence March,et al.  2016 , 2016, Affair of the Heart.

[21]  Tong Zhang,et al.  Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance , 2011, FAST.

[22]  Wei-Kuan Shih,et al.  Boosting the performance of 3D charge trap NAND flash with asymmetric feature process size characteristic , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[23]  Onur Mutlu,et al.  Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation , 2018, SIGMETRICS.

[24]  Y. Iwata,et al.  Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices , 2006, 2009 Symposium on VLSI Technology.

[25]  Andrew A. Chien,et al.  Tiny-Tail Flash , 2017, ACM Trans. Storage.

[26]  Gyoyoung Jin,et al.  Scaling and reliability of NAND flash devices , 2014, 2014 IEEE International Reliability Physics Symposium.

[27]  Jihong Kim,et al.  SARO: A State-Aware Reliability Optimization Technique for High Density NAND Flash Memory , 2018, ACM Great Lakes Symposium on VLSI.

[28]  Takashi Maeda,et al.  Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[29]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[30]  Andrew A. Chien,et al.  The Tail at Store: A Revelation from Millions of Hours of Disk and SSD Deployments , 2016, FAST.

[31]  Adam Silberstein,et al.  Benchmarking cloud serving systems with YCSB , 2010, SoCC '10.

[32]  Sungjin Lee,et al.  FlashBench: A workbench for a rapid development of flash-based storage devices , 2012, 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP).

[33]  Eun-seok Choi,et al.  Device considerations for high density and highly reliable 3D NAND flash cell in near future , 2012, 2012 International Electron Devices Meeting.

[34]  Donggun Park,et al.  Data retention characteristics of sub-100 nm NAND flash memory cells , 2003, IEEE Electron Device Letters.

[35]  Sungjin Lee,et al.  Dynamic Erase Voltage and Time Scaling for Extending Lifetime of NAND Flash-Based SSDs , 2017, IEEE Transactions on Computers.

[36]  Fei Wu,et al.  Program error rate-based wear leveling for NAND flash memory , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[37]  Onur Mutlu,et al.  HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness , 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[38]  Rui Mao,et al.  P-Alloc , 2017, ACM Trans. Embed. Comput. Syst..

[39]  Young-Ho Lim,et al.  A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995 .

[40]  Xu Li,et al.  A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[41]  Il Han Park,et al.  A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory , 2018, IEEE Journal of Solid-State Circuits.

[42]  Meng-Fan Chang,et al.  Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations , 2015, IEEE Journal of Solid-State Circuits.