A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate <; 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.

[1]  Azita Emami-Neyestanak,et al.  An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Byungsub Kim,et al.  A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[3]  John Bulzacchelli,et al.  A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Amir Amirkhany,et al.  A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Behzad Razavi,et al.  2.4 A 25Gb/s 5.8mW CMOS equalizer , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[6]  Chih-Kong Ken Yang,et al.  A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE , 2007, IEEE Journal of Solid-State Circuits.

[7]  Samuel Palermo,et al.  A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS , 2013, 2013 Symposium on VLSI Circuits.