Validating simulation model cycle times at Seagate Technology
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[1] A. Spence,et al. Capacity planning of a photolithography work cell in a wafer manufacturing line , 1987, Proceedings. 1987 IEEE International Conference on Robotics and Automation.
[2] S. J. Hood. Detail vs. simplifying assumptions for simulating semiconductor manufacturing lines , 1990, Ninth IEEE/CHMT International Symposium on Electronic Manufacturing Technology,Competitive Manufacturing for the Next Decade.
[3] John W. Fowler,et al. Supporting manufacturing with simulation: model design, development, and deployment , 1996, Winter Simulation Conference.
[4] K. Potti,et al. Using simulation to improve semiconductor manufacturing , 1997 .
[5] John W. Fowler,et al. Measurable improvements in cycle-time-constrained capacity , 1997, 1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023).
[6] Steven Brown,et al. Effective implementation of cycle time reduction strategies for semiconductor back-end manufacturing , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).
[7] E. Akcali,et al. Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication , 1996, Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium.
[8] Mansooreh Mollaghasemi,et al. Validation and verification of the simulation model of a photolithography process in semiconductor manufacturing , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).
[9] Navdeep S. Grewal,et al. Integrating targeted cycle-time reduction into the capital planning process , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).
[10] Reha Uzsoy,et al. Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication , 2000 .