A highly efficient CDMA power amplifier based on parallel amplification architecture

A highly efficient code division multiple access power amplifier of parallel amplification architecture exhibits power added efficiency of 17% and adjacent channel power ratio less than -51 dBc at an output power of 16 dBm. The output impedances of the low/high-power amplifier chains are very low because the collector impedances of the "OFF-state" power heterojunction bipolar transistors are low and the low impedances are transformed into even lower ones by low-pass output matching circuits. The low impedances are boosted up using a compact lumped /spl lambda//4 transmission line and the chains are operated independently without producing any significant performance degradation.

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