An FPGA Emulation Platform for Polar Codes

While polar codes are a promising candidate of error correcting codes for both fiber optical communication and data storage applications, it is very time consuming, or even infeasible, to evaluate the bit error rate (BER) performance of polar codes with the software Monte-Carlo simulation, since these applications have a stringent requirement for the BER as low as 10-12 to 10-15. In this paper, we propose an FPGA emulation platform to tackle this problem. Several features are added to improve the adaptability of our emulation platform, and these features also set our FPGA emulation platform apart from prior FPGA implementations for polar codes. First, our platform consists of the encoder, the channel model, and the decoder, and it supports two channel models: the additive white Gaussian noise (AWGN) channel and the binary symmetric channel (BSC). Furthermore, an embedded CPU and an AXI interface are integrated so that our platform can be reconfigured to test different codes without re-implementing the decoder. Finally, our decoder has a multi-mode feature, which not only provides a way to test the error performance of both successive cancelation algorithm and successive cancelation list algorithm with different list sizes, but also provides various tradeoffs between throughput and error performance.

[1]  Alexander Vardy,et al.  Fast Polar Decoders: Algorithm and Implementation , 2013, IEEE Journal on Selected Areas in Communications.

[2]  Alexander Vardy,et al.  List decoding of polar codes , 2011, 2011 IEEE International Symposium on Information Theory Proceedings.

[3]  Emre Telatar,et al.  On the rate of channel polarization , 2008, 2009 IEEE International Symposium on Information Theory.

[4]  Warren J. Gross,et al.  Increasing the Throughput of Polar Decoders , 2013, IEEE Communications Letters.

[5]  Emre Telatar,et al.  Polarization for arbitrary discrete memoryless channels , 2009, 2009 IEEE Information Theory Workshop.

[6]  Kai Chen,et al.  CRC-Aided Decoding of Polar Codes , 2012, IEEE Communications Letters.

[7]  Frank R. Kschischang,et al.  A Simplified Successive-Cancellation Decoder for Polar Codes , 2011, IEEE Communications Letters.

[8]  Jim Gray,et al.  Empirical Measurements of Disk Failure Rates and Error Rates , 2007, ArXiv.

[9]  Mehmet Ertugrul Çelebi,et al.  Code based efficient maximum-likelihood decoding of short polar codes , 2012, 2012 IEEE International Symposium on Information Theory Proceedings.

[10]  Paul H. Siegel,et al.  Polar codes for magnetic recording channels , 2015, 2015 IEEE Information Theory Workshop (ITW).

[11]  Erdal Arikan,et al.  A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Zifeng Wu,et al.  Polar Codes for Low-Complexity Forward Error Correction in Optical Access Networks , 2014 .

[13]  Anxiao Jiang,et al.  A study of polar codes for MLC NAND flash memories , 2015, 2015 International Conference on Computing, Networking and Communications (ICNC).

[14]  Kai Chen,et al.  Low-Complexity Sphere Decoding of Polar Codes Based on Optimum Path Metric , 2013, IEEE Communications Letters.

[15]  Pierre L'Ecuyer,et al.  Maximally equidistributed combined Tausworthe generators , 1996, Math. Comput..

[16]  Polina Bayvel,et al.  Replacing the Soft-Decision FEC Limit Paradigm in the Design of Optical Communication Systems , 2015, Journal of Lightwave Technology.

[17]  Alexios Balatsoukas-Stimming,et al.  An FPGA-based accelerator for rapid simulation of SC decoding of polar codes , 2015, 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

[18]  Bin Li,et al.  Parallel Decoders of Polar Codes , 2013, ArXiv.

[19]  Zhiyuan Yan,et al.  A Multimode Area-Efficient SCL Polar Decoder , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Wayne Luk,et al.  Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  S. Ravishankar,et al.  FPGA implementation of an advanced encoding and decoding architecture of polar codes , 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

[22]  Alptekin Pamuk,et al.  An FPGA implementation architecture for decoding of polar codes , 2011, 2011 8th International Symposium on Wireless Communication Systems.

[23]  Bin Li,et al.  Low-latency polar codes via hybrid decoding , 2014, 2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC).

[24]  Zhiyuan Yan,et al.  Symbol-Decision Successive Cancellation List Decoder for Polar Codes , 2015, IEEE Transactions on Signal Processing.

[25]  Garik Markarian,et al.  Performance of short polar codes under ML decoding , 2009 .

[26]  Erdal Arikan,et al.  Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels , 2008, IEEE Transactions on Information Theory.

[27]  Warren J. Gross,et al.  A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs , 2015, 2015 IEEE Workshop on Signal Processing Systems (SiPS).

[28]  Zhiyuan Yan,et al.  A High Throughput List Decoder Architecture for Polar Codes , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.