Design and integration considerations for end-of-the roadmap ultrashallow junctions

Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the 250–50 nm generations of complimentary metal-oxide-semiconductor ultralarge scale integration technology. The design of contacting and extension junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semiconductors off-state leakage specifications. A maxima in saturated drive current is observed for an intermediate extension junction depth (∼20 nm for 100 nm technology): shallower junctions lead to higher series resistance, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to depend on junction abruptness. For a perfectly abrupt junction, it is not necessary for the gate to overlap the junction. Performance depends on many parameters, including: overlap of gate to extension junctio...

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