Design and analysis of a new sub-threshold DTMOS SRAM cell structure

In this paper, we propose a novel dynamic threshold (DTMOS) based fully differential ten-transistor (10T) SRAM (Static Random Access Memory) cell suitable for sub-threshold operation. The structure has two inverters in addition to the conventional 6T standard cell. It provides better read current, increased read and hold static noise margins (SNM) and improved write time compared to a recently proposed sub-threshold SRAM cell. The stability of sub-threshold DTMOS SRAM to process variations is also investigated. The robust dynamic threshold based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners.

[1]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[2]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[3]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[4]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[5]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[6]  David Blaauw,et al.  A Sub-200mV 6T SRAM in 0.13μm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Kaushik Roy,et al.  A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Yong-Bin Kim,et al.  A Highly-Stable Nanometer Memory for Low-Power Design , 2008, 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems.

[9]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[10]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[11]  Kaushik Roy,et al.  A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology , 2008, 2008 IEEE Custom Integrated Circuits Conference.