Peak-to-Peak Ground Noise on a Power Distribution TSV Pair as a Function of Rise Time in 3-D Stack of Dies Interconnected Through TSVs

Supply grids of integrated chips are interconnected through through-silicon vias (TSVs) in modern design techniques to form a 3-D stack in vertical direction. The load on each chip is supplied through (power/ground) TSV pairs. Accurate estimation of power/ground noise on each TSV pair of a 3-D power distribution network is necessary for a robust power supply design. The worst case noise obtained with fast switching characteristics may not be significantly accurate. The behavior of power/ground noise as a function of rise time for an inductive power distribution TSV pair with decoupling capacitance, is investigated in this paper. An equivalent rise time corresponding to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. In addition noise sensitivity to decoupling capacitance and TSV inductance is evaluated as a function of rise time. We also discuss noise accumulation as a result of worst case damping factor in this paper.

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