Reduced scan shift: a new testing method for sequential circuits

This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences. In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible. For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors. Experimental results for ISCAS'89 benchmark circuits are given to show the effectiveness of this method.

[1]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[2]  Melvin A. Breuer,et al.  The BALLAST Methodology for Structured Partial Scan Design , 1990, IEEE Trans. Computers.

[3]  Janak H. Patel,et al.  Proofs: a fast, memory efficient sequential circuit fault simulator , 1991, DAC '90.

[4]  Melvin A. Breuer,et al.  Ordering storage elements in a single scan chain , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[5]  Irith Pomeranz,et al.  COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[6]  Ralph Marlett,et al.  Selectable Length Partial Scan: A Method to Reduce Vector Length , 1991, 1991, Proceedings. International Test Conference.

[7]  Jhing-Fa Wang,et al.  Overall consideration of scan design and test generation , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Kewal K. Saluja,et al.  An algorithm to reduce test application time in full scan designs , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Jau-Shien Chang,et al.  Test set compaction for combinational circuits , 1992, Proceedings First Asian Test Symposium (ATS `92).

[10]  R. Gupta,et al.  Configuring multiple scan chains for minimum test time , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[11]  Chen-Shang Lin,et al.  Test time reduction in scan designed circuits , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[12]  Chauchin Su,et al.  A serial scan test vector compression methodology , 1993, Proceedings of IEEE International Test Conference - (ITC).

[13]  Hiroyuki Higuchi,et al.  Compact Test Sequences for Scan-Based Sequential Circuits (Special Section on VLSI Design and CAD Algorithms) , 1993 .

[14]  Kozo Kinoshita,et al.  Test Sequence Generation for Sequential Circuits with Distinguishing Sequences (Special Section on VLSI Design and CAD Algorithms) , 1993 .

[15]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Irith Pomeranz,et al.  On compacting test sets by addition and removal of test vectors , 1994, Proceedings of IEEE VLSI Test Symposium.

[17]  Irith Pomeranz,et al.  Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..