A Novel Low Power Multiplexer-Based Full Adder

1-bit full adder circuit is a very important primitive cell in the design of Application Specific Integrated Circuits. This paper presents a novel lowpower multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charging recycling capability, this circuit has no direct connections to power supply nodes and the entire signal gates are directly excited by the fresh input signals, leading to noticeable reduction in short -current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it uses 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster. This new MBA-12T adder thereby, is a good primitive cell to build larger low power VLSI systems.

[1]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[2]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[3]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[4]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[5]  Yuke Wang,et al.  Design and analysis of 10-transistor full adders using novel XOR-XNOR gates , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[6]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.