Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity

Partial open defects in modern Static Random Access Memory (SRAM) address decoders are one of the main causes of small delays; these are hard to detect and may result in escapes and reliability problems. In addition, Aging failures - such as Bias Temperature Instability (BTI)-may worsen the situation and accelerate the degradation (i.e. increase the delay) and cause sooner field failures. This paper investigates the impact of partial opens and BTI in SRAM address decoders first separately and thereafter in a combined manner. Simulation results show that BTI impact strongly depends on the selected worldline, transistor location and addressing scheme; and it cause up to 14.27% additional delay. In addition, they show that partial opens, which do not cause hard faults and allow memory operations to pass correctly, contribute up to 23.65% additional delay. Combining these failure mechanisms reveals that the degradation can strongly be worsened and accelerate wear-out; an additional delay of up to 31.20% can be caused. This indicates the importance of incorporating appropriate design-for-reliability/testability schemes in order to guarantee the required lifetime of the memory system.

[1]  Manoj Sachdev.  Open Defects in CMOS RAM Address Decoders , 1997, IEEE Des. Test Comput..

[2]  Said Hamdioui,et al.  An experimental analysis of spot defects in SRAMs: realistic fault models and tests , 2000, Proceedings of the Ninth Asian Test Symposium.

[3]  S. Kundu,et al.  Test challenges in nanometer technologies , 2000, Proceedings IEEE European Test Workshop.

[4]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[5]  M. Raymond,et al.  22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell , 2008, 2008 IEEE International Electron Devices Meeting.

[6]  G. Groeseneken,et al.  From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[7]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[8]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[9]  Said Hamdioui,et al.  Memory Fault Modeling Trends: A Case Study , 2004, J. Electron. Test..

[10]  Said Hamdioui,et al.  Temperature dependence of NBTI induced delay , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[11]  K. Yamaguchi,et al.  The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[12]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[13]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[14]  Qiong Yang,et al.  Bmc Medical Genetics Genome-wide Association and Linkage Analyses of Hemostatic Factors and Hematological Phenotypes in the Framingham Heart Study , 2022 .

[15]  Phil Nigh,et al.  Test method evaluation experiments and data , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[16]  Shekhar Y. Borkar,et al.  Microarchitecture and Design Challenges for Gigascale Integration , 2004, MICRO.

[17]  Arnaud Virazel,et al.  Resistive-open defects in embedded-SRAM core cells: analysis and march test solution , 2004, 13th Asian Test Symposium.

[18]  Kaushik Roy,et al.  Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Said Hamdioui,et al.  Memory test experiment: industrial results and data , 2006 .

[20]  G. Groeseneken,et al.  Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.

[21]  Asim J. Al-Khalili,et al.  Analysis of Resistive Open Defects in Drowsy SRAM Cells , 2011, J. Electron. Test..

[22]  C. Cabral,et al.  A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[23]  Arnaud Virazel,et al.  ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions , 2006, J. Electron. Test..

[24]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[25]  Said Hamdioui,et al.  Opens and Delay Faults in CMOS RAM Address Decoders , 2006, IEEE Transactions on Computers.

[26]  Said Hamdioui,et al.  Modeling and mitigating NBTI in nanoscale circuits , 2011, 2011 IEEE 17th International On-Line Testing Symposium.