Nanoprobing SRAM Bit Cells with High-Speed Pulses

For a number of years, in-die SRAM transistors have been successfully probed using direct current (dc) nanoprobing to reveal faults for failure analysis and to verify in-die parametric performance for the engineering design loop.[1-5] These slow dc tests are needed for measuring subnanoampere gate and channel leakages. There has recently been interest in exploring the value of high-speed testing using a nanoprober. A well-known technique of high-speed pulse testing has been very useful for measuring the effects of self-heating in silicon-on-insulator devices, trapped charge in high-k dielectric material, and rapid testing that generates millions of waveforms per second.[6-8] All of these techniques were developed for use at the microscale. The reason these techniques have not been mainstream for nanoprobing is merely the perceived nanoscale barrier. Probing systems with high-speed capability are typically associated with the larger-scale optical-based microprobing systems. Historically, nanoprobing systems have been optimized for dc testing, but there is not a significant hurdle to their use in high-speed testing. This paper describes the use of a scanning electron microscope (SEM)-based nanoprobing system equipped with high-speed testing capability. The system, which is capable of 10 ns rise and fall times, is used to characterize in-die SRAM bit cells. A single high-speed test, taken at the bit cell level, determines the most likely failing transistor. This technique decreases fault localization time, and because the test is done at metallization layer 1, it decreases the possibility of deprocessing past the fail.