Virtual prototyping of floating point units

Virtual prototyping is a key technology for design space exploration, design verification, code development and testing of new systems on chip. For processors, either general purpose, multi and manycore or GPUs, the availability of powerful floating point units has now become mandatory in a lot of markets. However, implementing a fast and accurate floating point unit virtual prototype is not easy, even if host and target processors are IEEE 754 compliant. The goal of this paper is not to propose a definitive solution to this problem, but to draw the attention of the virtual prototyping community to it. To that aim, we study two solutions that form a compromise between speed of virtual prototype execution and computation accuracy.

[1]  Andreas Gerstlauer,et al.  The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Andreas Gerstlauer,et al.  Abstract system-level models for early performance and power exploration , 2012, 17th Asia and South Pacific Design Automation Conference.

[3]  Nicholas Nethercote,et al.  Valgrind: a framework for heavyweight dynamic binary instrumentation , 2007, PLDI '07.

[4]  Wolfgang Rosenstiel,et al.  Source level performance simulation of GPU cores , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Frédéric Pétrot,et al.  On MPSoC Software Execution at the Transaction Level , 2011, IEEE Design & Test of Computers.

[6]  Ittetsu Taniguchi,et al.  Cache Simulation for Instruction Set Simulator QEMU , 2014, 2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing.

[7]  Eugenio Villar,et al.  Fast data-cache modeling for native co-simulation , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[8]  Guillaume Melquiond,et al.  Emulation of a FMA and Correctly Rounded Sums: Proved Algorithms Using Rounding to Odd , 2008, IEEE Transactions on Computers.

[9]  David Defour,et al.  Barra: A Parallel Functional Simulator for GPGPU , 2010, 2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

[10]  G. Melquiond,et al.  Some issues related to double rounding , 2013 .

[11]  Vincent Lefèvre,et al.  On the Computation of Correctly-Rounded Sums , 2009, 2009 19th IEEE Symposium on Computer Arithmetic.

[12]  Donald E. Knuth,et al.  The art of computer programming. Vol.2: Seminumerical algorithms , 1981 .

[13]  Frédéric Pétrot,et al.  Automatic instrumentation of embedded software for high level hardware/software co-simulation , 2009, 2009 Asia and South Pacific Design Automation Conference.

[14]  Jörg Henkel,et al.  Fast and accurate cache modeling in source-level simulation of embedded software , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).