Soft error mitigation through selection of noninvert implication paths
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[1] Ming Zhang,et al. Combinational Logic Soft Error Correction , 2006, 2006 IEEE International Test Conference.
[2] B. Narasimham,et al. Quantifying the Effect of Guard Rings and Guard Drains in Mitigating Charge Collection and Charge Spread , 2008, IEEE Transactions on Nuclear Science.
[3] S. Bhanja,et al. Selective Redundancy: Evaluation of Temporal Reliability Enhancement Scheme for Nanoelectronic Circuits , 2008, 2008 8th IEEE Conference on Nanotechnology.
[4] Narayanan Vijaykrishnan,et al. SEAT-LA: a soft error analysis tool for combinational logic , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[5] Yiorgos Makris,et al. Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires , 2008, IEEE Transactions on Reliability.
[6] D. Sylvester,et al. Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[7] Nur A. Touba,et al. Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[8] W. T. Holman,et al. Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes , 2007, IEEE Transactions on Nuclear Science.
[9] A.F. Witulski,et al. HBD layout isolation techniques for multiple node charge collection mitigation , 2005, IEEE Transactions on Nuclear Science.
[10] W. T. Holman,et al. Layout Technique for Single-Event Transient Mitigation via Pulse Quenching , 2011, IEEE Transactions on Nuclear Science.
[11] M. Nicolaidis,et al. Evaluation of a soft error tolerance technique based on time and/or space redundancy , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).
[12] P. Eaton,et al. Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[13] C P Jain. Circuit Level Design Approaches for Radiation- Hard Digital Electronics , 2014 .
[14] Kewal K. Saluja,et al. Gate input reconfiguration for combating soft errors in combinational circuits , 2010, 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W).
[15] David Blaauw,et al. Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Liyi Xiao,et al. Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[17] Fang Liu,et al. Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique , 2006, DFT.